A STUDY OF FAILURE MECHANISMS IN SILICON PLANAR EPITAXIAL TRANSISTORS.
Abstract
A gated planar diode was used on a test structure to study the effect of charges on the oxide and to determine oxide sheet resistivities. Important factors found to affect sheet resistivity were moisture, ionic contamination, and temperature. Order of magnitude calculations show that typical sheet resistivities on the order of 10 to the 19th power ohms at 200 to 300 C are low enough to cause life test (HTRB) failure. Under these conditions, for a device of FT-1312 dimensions, inversion layers could reach the edge of the die in calculated times on the order of 1000 hours. Applying a metal-over-oxide (MOS) model, channel currents of the magnitude and type seen thus far on HTRB life tests of the FT-1312 can be explained by recombination-generation processes in the surface space-charge region associated with the collector junction. The lattice strain induced in silicon by the diffusion of impurities contributes to small recombination currents in p-n junctions. For shallow diffused structures (FT-1312), lattice deformation was found to be low since the total quantity of diffused impurities is below a critical concentration. Gold-aluminum diffusion couples were aged at elevated temperatures (200 to 300C) and none of the previously reported causes of bond failure accurately described the aging process. The ball bonds lost very little strength.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1966
- Accession Number
- AD0487527
Entities
People
- A. S. Grove
- E. H. Snow
- H. Sello
- I. A. Blech
- J. D. Fitzgerald