ENGINEERING SERVICES ON TRANSISTORS.
Abstract
This report discusses work on a 6-Gc low-power germanium transistor and integrated circuit devices. Status of the work on a 6-Gc low-power germanium transistor is reported. Techniques for fabricating the oxide-photoengraved planar structure are evaluated. Electrode stripes of 1 micron in width and submicron electrode spacings appear feasible. The equivalent circuit parameters of four transistor structures are analyzed. Preliminary studies of special wafermounting structures to minimize parasitic effects for compatible circuit installation are reported. Results of multiple-chip integrated circuits using specially designed transistors are described. Storage times have been reduced and measured propagation times are lower. Both DCTL and LLL are considered. A paper study is presented which explores various ways of integrating a four-bit adder within the limitations of the ten-pin TO-5 header. It was found that the number of cans can be halved if relatively complex specially tailored packages are used instead of simple two-gate or three-gate packages. An integrated circuit scheme involving a glass-cemented mosaic of silicon is described. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 30, 1964
- Accession Number
- AD0600099
Entities
People
- D. J. D'stefan
- J. E. Iwersen
- J. J. Chang
- J. Kocsis
- Robert G. Edwards