DEVELOPMENT OF INTEGRATED CIRCUITS UTILIZING COMPLEMENTARY TRANSISTORS.
Abstract
Complementary pnp-npn bipolar integrated circuits can be fabricated by diffusing from a doped oxide source that is deposited on the silicon surface. This technique, wherein the doped oxide is deposited at a low temperature by the thermal oxidation of SiH4, makes possible the simultaneous diffusion of oppositely doped impurities, so that 'mirror image' pnp-npn characteristics can be achieved. Substrate preparation, to maintain isolation between devices while providing proper collector regions for each, can be achieved by combining RCA's 'handle' oxide isolation technique with pocket etch and epitaxial refill techniques. Transistor masks were designed and fabricated, preliminary calibration of the doped oxide systems were established for the required n and p concentrations, standard work stations for silane deposition systems were designed and ordered and single devices were fabricated using doped oxide diffusions. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 30, 1965
- Accession Number
- AD0623510