PROGRESS REPORT ON THE NEBULA COMPUTER.

Abstract

A medium speed, serial digital computer was constructed using glass delay lines circulating at 22 mc. as memory. An arrangement of information within the 22 mc. memory allows a simple interface with the 340 kc. arithmetic unit, which results in an effective zero latency time and provides possibilities for an associative memory. The arithmetic unit has a command structure similar to large parallel machines and uses flip-flop arithmetic and control registers throughout. All hardware development has been aimed toward the concept of easy modification, elaborate console controls for effective man-machine interaction, and low cost. (Author)

Document Details

Document Type
Technical Report
Publication Date
Jan 14, 1966
Accession Number
AD0633364

Entities

People

  • D. B. Shepard
  • G. A. Hoselton
  • J. A. Boles
  • P. T. Rux
  • W. A. Nickodemus

Organizations

  • Oregon State University

Tags

DTIC Thesaurus Topics

  • Arithmetic
  • Arithmetic Units
  • Computers
  • Computing Devices
  • Content Addressable Memory
  • Delay Lines
  • Digital Computers

Readers

  • Computer Engineering
  • Parallel and Distributed Computing.
  • Systems Analysis and Design