A HIGH-SPEED SERIAL ADDER OF THE INTERMDIATE TYPE,
Abstract
The article examines a high-speed binary serial adder of the intermediate type that is connected with a memory device of the parallel type. For the formation of a digital sum the adder forms the functions E(a, b), E'(a' b') and Q sub s(aE). The formation of the function Q sub s and the transfer for the next cycle occurs simultaneously. A special trigger of the digital sum preserves the digit of one sum until the Q sub s signal is received, after which its state is reversed and the digital sum S is fixed. It is proposed that the application of this device will remove the basic efficiencies of the existing devices of this type. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 05, 1966
- Accession Number
- AD0646506
Entities
People
- M. G. Gogoberidze
- T. V. Dolidze
Organizations
- National Air and Space Intelligence Center