SYNTHESIS AND MINIMIZATION OF DIAGRAMS WITH REAL LOGICAL ELEMENTS OF THE TYPE AND-NOT OR OR-NOT,
Abstract
By real logical elements is meant elements which have a time of operation which is not equal to zero. In the making of diagrams that are not constructed on such elements, at the time of transitions from cycle to cycle there may occur contests leading sometimes to errors in the working of the diagram. To the contests which arise in some transitions there corresponds in the logical formula, which describes the working of the diagram, the disjunction or conjunction of two or more terms whose value at least for one in this transition changes from 0 to 1 and for at least one from 1 to 0. With the presence of such terms the contests are termed hazardous. In this article there is provided a method for the synthesis of the diagrams on real AND-NOT or OR-NOT, which is based on the use of the same algorithms.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 10, 1967
- Accession Number
- AD0666735
Entities
People
- E. A. Yakubaitis
- N. P. Shmaukstel
Organizations
- National Air and Space Intelligence Center