A CYCLIC CHECK COMPUTER FOR ERROR DETECTION

Abstract

The report discusses the design and use of equipment built to aid intercomputer communicatitions via serial-synchronous data transmission techniques. The interface described computes on a character-by-character basis, a cyclic redundancy block checksum which is appended to outgoing or checked against incoming messages. This hardware techniques reduces checksum computation on a small computer from several hundred microseconds per character to only several microseconds; a reduction that is necessary if more than several 201 type data modems are to be operated simultaneously under control of a single processor. Basic design objectives and decisions are described first. A brief overall system description with background information is then followed by programming considerations and detailed descriptions of the checksum computer logic. Finally diagnostic software and wirewrap documentation is provided for maintenance and/or reproduction purposes.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1968
Accession Number
AD0671758

Entities

People

  • Kenneth E. Burkhalter

Organizations

  • University of Michigan

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Abstracts
  • Circuits
  • Classification
  • Computations
  • Computer Programming
  • Computers
  • Data Transmission
  • Decoding
  • Detection
  • Instructions
  • Logic
  • Maintenance
  • Microsecond Time
  • Personality
  • Pulse Amplifiers
  • Security
  • Shift Registers

Fields of Study

  • Computer science

Readers

  • Computer Programming and Software Development.
  • Computer Science.
  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.