A COMBINATIONAL ARITHMETIC FUNCTION GENERATION SYSTEM,
Abstract
The continuing reduction of the size and cost of microelectronic logic elements encourages the utilization of more complex logic nets in digital computers. In arithmetic processors, because of the application of these complex logic nets, the replacement of sequential logic nets by their combinational equivalents and the substitution of programmed software subroutines by hardware function generators are to be economically justified in the near future. The kernel of this combinational function generation system is embodied in the design of a single building block and the specification of combinational arithmetic nets. This building block is designed at the arithmetic level, employing the redundant signed-digit number system, in order to take full advantage of the complexity offered by microelectronics on a single chip. A combinational arithmetic net, composed of an acyclic array of the arithmetic building block, is oriented in such a fashion that a given function can be approximated with accuracy, cost, and speed adjustable. An economic alternative to this locally combinational arithmetic net is the pipelined combinational arithmetic net which is composed of a totally combinational arithmetic subnet and a sequential subnet with feedback loops introduced. The pipelined combinational arithmetic net is found to be particularly suitable for evaluating Chebyshev series which is an important approach to approximating a wide variety of functions. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1968
- Accession Number
- AD0672586
Entities
People
- Chin Tung
Organizations
- University of California, Los Angeles