PUSH DOWN LIST MEMORY (PUDL).
Abstract
The principles of operation of Domain Tip Propagation Logic (DTPL) and its application to thin film all-magnetic logic have been described in previous papers. The controlled growth and interaction of domain tips, confined to narrow, low coercive force propagation channels within a film element of generally high coercive force, were shown capable of being utilized to perform all digital logic functions and to implement high-speed, bidirectional magnetic shift registers. In order to determine the feasibility of a DTPL implementation of a Push Down List Memory (PUDL), an 8 list, 25 word/list, 13 bit/word feasibility model was designed, constructed, and demonstrated. This report describes work which was carried out on the design of the feasibility model. Investigations were made on the basic PUDL thin-film shift register structure as well as the associated conductor patterns. Drive and sense electronics and the PUDL system has been studied and evaluated. The general feasibility of the DTPL implementation of a Push Down List Memory is demonstrable, the question of the cycle time, a factor, which requires additional work and optimization of the thin film elements. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 1968
- Accession Number
- AD0676659
Entities
People
- John Veronelli
- Michael J. Marino