ON THE REPRESENTATION OF DIGITAL FAULTS,
Abstract
A new representation for faults in combinational digital systems is presented. Faults which are inherently indistinguishable are identified and combined into classes. The behavior of the circuit under fault conditions is represented in terms of these classes. This results in a description of the faulty circuit by means of Boolean equations which are readily manipulated for the purpose of test generation or fault simulation. A connection graph interpretation of this fault representation is discussed. Heuristics methods for the selection of efficient tests without extensive computation are derived from these connection graphs. The fault classes form a geometric structure which effectively subdivides the original circuit into fanout-free segments. This fanout-free characteristic allows a simplified analysis of multiple fault conditions. It is proven that the detection of a small subset of multiple faults guarantees the detection of all multiple faults. For any given circuit, the faults in this subset may be identified with a minimum of computation. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1969
- Accession Number
- AD0688836
Entities
People
- Donald Ralph Schertz
Organizations
- University of Illinois Urbana–Champaign