RESEARCH AND DEVELOPMENT OF HIGH SPEED PROCESSOR ARRAYS.

Abstract

Preliminary design for a processor master array chip containing 80 gates and 16 reference bias cells has been completed. Functioning read-only memory arrays were successfully fabricated. A flexible technique for programming these ROM's at the chip level has been developed and demonstrated. Speed-power studies aimed at obtaining optimum performance in the processor arrays are continuing. Yield improvement studies are continuing. This effort includes the investigation of the applicability of the CDI process to high-speed ECL and the design of a complex multilevel process test chip for characterizing and monitoring multilevel interconnection processes and structures. Test vehicles are being fabricated for investigating face-down bonding and aluminum beam lead technologies. Reliability data are presented for high-speed two-level arrays.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1969
Accession Number
AD0694555

Entities

Organizations

  • Massachusetts Institute of Technology

Tags

DTIC Thesaurus Topics

  • Air Force
  • Aluminum
  • Assembly
  • Beam Lead Technology
  • Beam Leads
  • Computer Programming
  • Diagrams
  • Epitaxial Growth
  • Fabrication
  • Microcircuits
  • Microelectronics
  • Monitoring
  • Schematic Diagrams
  • Test And Evaluation
  • Test Vehicles
  • United States
  • Vehicles

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Systems Analysis and Design