STEADY STATE AND TRANSIENT ANALYSIS OF A DIGITAL BIT-SYNCHRONIZATION PHASE-LOCKED LOOP,
Abstract
A digital bit-synchronization phase-locked loop employing binary phase error quantization and sequential loop filtering is described. Steady state and transient performance is analyzed in the presence of white Gaussian noise. Bit error rates and effective loop bandwidths are also given. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 01, 1970
- Accession Number
- AD0705007
Entities
People
- James R. Cessna
Organizations
- University of Iowa