ERROR-TOLERANT SEQUENTIAL CIRCUIT DESIGN USING ERROR-CORRECTING CODES.
Abstract
Redundancy is an important technique in the design of error-tolerant electronic computers. Many redundant schemes have been proposed and developed for combinational circuits; this study is directed toward redundant schemes for general computing circuits, specifically, sequential circuits. The design of error-tolerant sequential circuits using error-correcting codes is approached from a practical as well as theoretical viewpoint with the language of sequential machine theory and coding theory being unified into a foundation for error-tolerant sequential machine theory. Various synthesis procedures are presented for synchronous sequential circuits which tolerate transient errors and permanent failures. The effectiveness of these procedures is evaluated in detail for a simple example, the eight-state binary counter. Using exponential failure distributions, it is shown that reliability is significantly improved for mission times of long duration for this example. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1970
- Accession Number
- AD0710210
Entities
People
- Ronald Wayne Larsen
Organizations
- University of Southern California