Research and Development of High Speed Processor Arrays
Abstract
The report describes program progress during the eight-month extension period of a research and development program directed toward the development of high performance, digital MSI-LSI microcircuits and their application in feasibility studies of high speed data processing systems. The tasks of this report period included the fabrication of a high speed 80-gate array with three levels of metallization and the performance evaluation of a high speed (<1.0 nsec), low power (<15 mW), ECL gate design, for various on-chip gate loading conditions. Both tasks were completed. Also required was the fabrication and delivery of three different, custom, ECL Two-Bit Fast Carry Gated Adder microcircuits (two levels of metallization) for application in a high speed 17 x 17 Array Multiplier. A total of 136 adders are required for the multiplier. The required number of adders were delivered, and the multiplier which was assembled using those adders functioned properly. The time required for the multiplier to perform its function was measured to be 40 nsec, a 10-nsec improvement over the expected time.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 1970
- Accession Number
- AD0714080
Entities
Organizations
- Massachusetts Institute of Technology