Enhancing Testability of Large-Scale Integrated Circuits Via Test Points and Additional Logic.
Abstract
The work studies methods of using test points in conjunction with additional logic gates to provide an easy means to set or check the state. Among several logic modification schemes, the most useful appears to be one in which a single test point can be used to switch the circuit into a second mode of operation, a 'test mode'. In the test mode the flip-flops are reconnected to form a shift register, so that the state can be easily set or checked: however it is not possible to guarantee correct operation in this mode in the presence of a fault. After an initial state has been set, the circuit can be switched to normal mode for a test, then returned to the test mode so that the final state can be checked. For a synchronous sequential circuit whose state can be easily set or checked, the problem of generating a test to detect a given logical fault reduces to the problem of generating a test for the fault in a purely combinational network of similar complexity. The cost of such circuit modifications was analyzed. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1970
- Accession Number
- AD0714511
Entities
People
- Michael J. Y. Williams
Organizations
- Stanford University