Derivation of Minimum Test Sets for Unate Logical Circuits.
Abstract
A derivation of tests sets S sub 0 and S sub 1 for irredundant unate logical circuits is presented. It is shown that these sets (S sub 0 and S sub 1, respectively) detect all stuck-at-0 and stuck-at-1 faults in all realizations with no internal inverters of a given unate function. They can be obtained easily from the minimum sum and minimum product forms, from a Karnaugh map or from a Hasse diagram of the function. These sets are minimum in the sense that there is no set with a smaller number of elements that detects all faults in the class of realizations of a logical function. In particular, it is found that a two-level AND-OR (OR-AND) network needs all the tests in S sub 0 (S sub 1). (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 1970
- Accession Number
- AD0720330
Entities
People
- Rodolfo Betancourt
Organizations
- Stanford University