On the Design of Diagnosable Asynchronous Sequential Machines,
Abstract
Asynchronous state assignment methods are discussed and certain concepts based on these methods are defined. The discussion includes a review of the two race-free assignment methods developed by Huffman, and a detailed review of the USTT assignment method developed by Tracey. The concepts of transition cube, controlling variable, stationary variable and switching variable are defined. Asynchronous circuits realized with flip-flop or delay memories under USTT and race-free state assignments are examined to determine their vulnerability to critical races, hazards and oscillations under faults. Design rules are developed to make circuits invulnerable to most oscillations. It is shown that the vulnerability of virtually all circuits to critical races under faults cannot be removed without adding redundant state variables. Finally a fault tolerant circuit design is proposed. Using redundancy and a special type of logical realization, the fault behavior of the circuit is constrained such that the set of states which the circuit can take under faults is limited to a small number. A check circuit which will indicate the presence of a fault in the sequential circuit is included. This circuit consists of three gates and can be diagnosed for faults with two tests. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1971
- Accession Number
- AD0732475
Entities
People
- William Wise Patterson
Organizations
- University of Illinois Urbana–Champaign