On Round-Off Error of Floating-Point Addition with Guard Digits,

Abstract

The assumption of double precision binary arithmetic operation is often made in the analysis of the finite word effect on digital signal processors. Some recent computers, such as those in the IBM 360 series, use radix 16 and single precision with guard digit in floating-point addition. In this paper, a bound on the round-off error for floating-point addition in single precision with guard digits is derived. Comparison with double precision addition is made. (Author)

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1971
Accession Number
AD0736519

Entities

People

  • Bede Liu
  • Toyahisa Kaneko

Organizations

  • Princeton University

Tags

DTIC Thesaurus Topics

  • Arithmetic
  • Binary Arithmetic
  • Computers
  • Cooperation
  • Mathematics
  • Precision

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.