Digital Logic Simulator.

Abstract

Digital Logic Simulator (DLS) is a CDC 6600 computer program which simulates synchronous and asynchronous networks of digital logic elements. It is used at Air Force Institute of Technology to verify digital logic designs. DLS uses a state variable model which associates time delays with all elements. Thus, the effects of propagation delays on circuit behavior can be analyzed. DLS has four operation modes which allow the user to test circuits at various levels of complexity. A complete users manual is included in the thesis which describes the detailed features, capabilities, and language specifications for DLS. (Author)

Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1971
Accession Number
AD0736827

Entities

People

  • John R. Niederhauser

Organizations

  • Air Force Institute of Technology

Tags

DTIC Thesaurus Topics

  • Air Force
  • Computer Programs
  • Computers
  • Control Simulators
  • Language
  • Logic
  • Logic Elements
  • Simulations
  • Simulators
  • Specifications

Fields of Study

  • Computer science

Readers

  • Computer Science.
  • Integrated Circuit Design and Technology.
  • Mathematical Modeling and Probability Theory.