A Parallel Arithmetic Unit,
Abstract
A parallel arithmetic unit for digital computers is fitted with two pairs of registers, each divided into a digit sum register and a digit transfer register. Each register has on its input AN and GATE which lies in a feedback circuit to input elements of the register in the other pair, AN and GATE to carry out the logic operations, and a three input adder. The clear signals are passed to each and GATE and adder through control wires. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 04, 1972
- Accession Number
- AD0736895
Entities
People
- A. A. Sokolov
- A. V. Avaev
- I. D. Vizun
- M. A. Golovina
- V. N. Laut
Organizations
- National Air and Space Intelligence Center