Another Associative Processor.
Abstract
The logical design of an associative processor (AP), which has evolved from the design previously reported in NRL Report 6961, has now been oriented toward the requirements of the Advanced Avionic Digital Computer (AADC) under development by the Naval Air Systems Command. The AP is a bytevariable processor with multifield search, arithmetic, and logical capability. Data flow within the AP is a vertical trickle. Data for each word is fed in from the word above and fed out to the word below. The output may be the same as the input (functionally equivalent to broadcast), may be the contents of the word itself, or may be some function of the input and the word contents. A CMOS hardware implementation of the AP design is being tested, and preliminary results indicate that some hardware revisions will be necessary. Questions of AP control have been considered, and the details will be worked out through use of a software simulation. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 30, 1971
- Accession Number
- AD0737188
Entities
People
- John E. Shore
- Terry L. Collins
Organizations
- United States Naval Research Laboratory