A Class of Testable Gate Network Realizations for Logic Functions.

Abstract

By assuming that the functions realized by certain subnetworks of certain gate networks realizing an arbitrary logic function are known, techniques to derive tests to detect faults in these networks are derived. (Author)

Document Details

Document Type
Technical Report
Publication Date
May 01, 1972
Accession Number
AD0745742

Entities

People

  • Sudhakar M. Reddy

Organizations

  • University of Iowa

Tags

DTIC Thesaurus Topics

  • Adaptive Control Systems
  • Adaptive Systems
  • Automation

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.