Electrical Overstress Failures in Silicon Devices

Abstract

Experimental evidence gathered from overstressing test patterns is presented to substantiate a mechanism proposed by the author for surface overstress failures (surface zaps). The mechanism involves field enhanced migration of liquid along a line determined by both crystal and electric fields. Migration is initiated by field enhanced breakdown from a defect or precipitate in the silicon which leads to current filament formation and a rise in temperature above the eutectic for Al-Si or Au-Si. It is demonstrated that with titanium contacts, surface shorts are eliminated. Graphs are given which show the relationship between breakdown voltage and electrode spacing and between maximum power dissipation and electrode spacing for aluminum contacts to 5 ohm- cm n-type and 0.5 ohm-cm p-type silicon. Oxidation temperature is identified as a factor which affects zap sensitivity as well.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1972
Accession Number
AD0747795

Entities

People

  • Clyde H. Lane

Organizations

  • Rome Laboratory

Tags

DTIC Thesaurus Topics

  • Circuits
  • Crystals
  • Electric Fields
  • Electronics
  • Failure Analysis
  • Failure Mode And Effect Analysis
  • Grain Growth
  • High Temperature
  • High Voltage
  • Integrated Circuits
  • Low Temperature
  • Materials
  • Metal-Semiconductor Junctions
  • Modules (Electronics)
  • Photographs
  • Reliability
  • Temperature Gradients

Readers

  • Semiconductor Device Technology
  • Software Engineering
  • Thin Film Deposition Science.

Technology Areas

  • Space
  • Space - Hall-Effect Thruster