On Generating Near Minimum Test Sets.

Abstract

A computerized algorithm for generating near minimum test sets for fault detection in combinational logic circuits is presented. The advantages of the approach in this algorithm over classical techniques are shown. The algorithm is then described and illustrated in great detail. Two software implementations of the algorithm are also given. Finally, comparisons and contrasts between this algorithm and other similar ones are described. (Author)

Document Details

Document Type
Technical Report
Publication Date
Aug 31, 1973
Accession Number
AD0768804

Entities

People

  • B. D. Carroll
  • John T. Ellis

Organizations

  • Auburn University

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Circuits
  • Contrast
  • Detection
  • Logic
  • Logic Gates
  • Test Sets

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computational Modeling and Simulation