Residual Saw Damage in Silicon Wafers and Its Influence on MOS Capacitance Relaxation

Abstract

Residual saw damage in silicon surfaces and its influence on MOS capacitance relaxation is discussed. Experiments are conducted to gain information on the influence of silicon process parameters on MOS capacitance relaxation. Process parameters investigated include: crystal slicing, wafer cleaning and wafer polishing. The main results of this investigation include evidence about saw damage in the silicon surface and its variation with different slicing and polishing procedures. It is also found that the amount of saw damage is larger in wafers cut from the tail-end relative to wafers cut from the seed-part of the crystal. Based on the results obtained, recommendations are made about future activities of the contract work.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1973
Accession Number
AD0768959

Entities

People

  • Guenter H. Schwuttke

Organizations

  • International Business Machines Corporation (Armonk, NY)

Tags

DTIC Thesaurus Topics

  • Capacitance
  • Commerce
  • Contracts
  • Crystals
  • Czochralski Crystals
  • Electrical Measurement
  • Electron Microscopy
  • Electrons
  • Materials
  • Measurement
  • Microscopes
  • Microscopy
  • New York
  • Polishing
  • Residuals
  • Security
  • Transmission Electron Microscopy

Fields of Study

  • Materials science

Readers

  • Semiconductor Device Technology
  • Structural Health Monitoring of Composite Structures.