Analysis and Simulation of Parallel Sequential Decoding.
Abstract
The document describes the implementation of a sequential decoder on a PDP-11 computer and presents a preliminary evaluation of decoder performance using a buffer allocation scheme modified to improve the use of buffer memory to minimize the probability of overflow. The modified decoder consists of two decoding processors operating on two half-size buffers. Input blocks are placed in the first available buffer, thus allowing a noisy block to remain in a buffer for a longer period than would normally be available with a single buffer and processor. A net gain for the modified system, due to lower probability of failure caused by buffer overflow, is indicated. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 29, 1973
- Accession Number
- AD0773098
Entities
People
- J. G. Dodds
Organizations
- Naval Information Warfare Systems Command