FAILURE MECHANISMS IN SEMICONDUCTOR DIODES
Abstract
The report is primarily concerned with the structuring, refining and verification of a Deterministic Model for diode failure. The Deterministic Model is presently separated into two portions; reverse bias degradation and forward bias degradation. The forward bias portion of the model proved to be more complex than the reverse bias portion. The following points were determined, and are discussed in this report: The temperature and pressure used in the sealing process have a major effect in the degradation response pattern; the degradation patterns following the sealing process, forward current stresses and at very high temperature stress at zero bias are identical; the degraded devices, which had been stressed in the sealing process, exhibited microplasma light emission, low amplitude microplasma noise pulses and reverse voltage walkout; the observed failure mechanisms seem to be surface, rather than bulk, related phenomena; there is evidence to indicate that the model should be based on the high temperature decomposition of a compound into components, at least one of which is active in increasing the surface electron concentration, the planned test matrix to complete the structuring, verification and refinement of the model; a summary of the failure analysis effort performed to date on this portion of the model.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1966
- Accession Number
- AD0802124
Entities
People
- Byron L. Blair
Organizations
- General Electric