DESIGN OF THE G-21 MULTI-PROCESSOR SYSTEM,
Abstract
During the summer of 1963, a multi-processor version of the CDC G-20 (the G-21) was developed for the Computation Center of Carnegie Institute of Technology. The purpose was to double the memory capacity and processing speed of the existing G-20 system. Since then, the system has continued to evolve as the needs of the Computation Center continue to grow. The purpose of this paper is to describe the memory control electronics which underlie memory time-sharing. The important related engineering problems are discussed in the terms of the current G-21 system. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 26, 1965
- Accession Number
- AD0804037
Entities
People
- Jesse T. Quatse
Organizations
- Carnegie Institute of Technology