DEVELOPMENT OF A LOW-COST MEDIUM-SPEED MASS RANDOM-ACCESS MEMORY

Abstract

The concept of a nonmechanical, mass, random access, plated-wire memory has been validated in this phase of the continuing U.S. Air Force program. The memory model fabricated for this contract has 10,000,000-bit positions housing over 2.3 megabits of plated wire. Of these bits, 32,768 4-bit words have been exercised with a memory exerciser. The following characteristics of the plated-wire mass memory have been demonstrated: Nondestructive readout (NDRO); Selection in the bit dimension to minimize electronics costs; Simple mechanical plane configuration; Random access, and Electrical alterability. The final test of the plane revealed some defective areas which resulted from the large surface area. Making a smaller plane would easily eliminate this condition. All the objectives of the program have been achieved, including the projected production cost of less than $0.01 per bit. The contractor feels that as a result of this program, the building of a mass 1 x 10 to the 8th power-bit, random access, plated-wire memory is economically feasible and well within the state-of-the-art.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1967
Accession Number
AD0809200

Entities

People

  • C. Chong
  • D. K. Hanson
  • R. Mosenkis

Organizations

  • Sperry Corporation

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Air Force
  • Amplifiers
  • Construction
  • Contractors
  • Contracts
  • Current Regulators
  • Electronic Circuits
  • Electronics
  • Fabrication
  • Integrated Circuits
  • Logic
  • Logic Gates
  • Magnetic Films
  • Magnetic Materials
  • Power Supplies
  • Production
  • Semiconductors

Readers

  • Aerospace Research.
  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems