SPEED BUFFERING AND DIGITAL COMBINING TECHNIQUES.
Abstract
A complete logic diagram was implemented for the transmitter and receiver of the digital combiner. Critical areas were discussed in detail. Among them were (a) the elastic store (b) the frame and reframe time and the choice of the type of logic elements for 10 megabit operation.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1967
- Accession Number
- AD0813118
Entities
People
- G. F. Dooley
- R. A. Cecka