MANUFACTURING METHODS FOR CRYOELECTRIC MEMORIES.
Abstract
Work concerns operational cryoelectric memory planes of a bit capacity of about 250,000 on a 4.5-in. x 5.4-in. substrate. Arrays of loop cell type C design at a density of 6,500 cells/sq in. and a 6000-bit capacity were fabricated, evaluated, and utilized to construct a 10 to the 4th power-bit hybrid a,b memory system. This system, including the interface networks amplifiers, detectors, decoders, drivers, timing logic, strobe circuits, etc., was completed, operated, and evaluated during this phase. The data from this 10 to the 4th power-bit hybrid a,b system provided valuable cell and array design information for the large quarter-million-bit plane objective.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 1967
- Accession Number
- AD0822671
Entities
People
- F. C. Brunner
- H. G. Scheible
- John J. Carrona
- R. A. Gange