SPEED BUFFERING AND DIGITAL COMBINING TECHNIQUES.
Abstract
The report contains comparative analysis of bit stuffing techniques, logic design of a 9.37 Mbs system, complete design and implementation of a 2.418 Mbs system, simulated data sources, error correlators and recommendations for an order wire. It also discusses ways of improving the design of the voltage controlled oscillator so that jitter produced can be tolerated by digital repeaters. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1968
- Accession Number
- AD0826377
Entities
People
- D. E. Peugh
- R. A. Cecka