ELEMENT DEVELOPMENT FOR ADVANCED ASSOCIATIVE MEMORIES.
Abstract
An associative memory, of enhancement insulated-gate complementary field-effect transistors, has been developed and partially tested. A typical 16-transistor cell dissipates 10-microwatt standby power and 1-mW switching power at 1-MHz 10-V operation. Masked evaporation in vacuum has been used to fabricate an experimental associative memory array consisting of enhancement complementary polycrystalline thin-film transistors. Such TFT's have thus been evaporated at close proximity onto a common substrate during a single vacuum cycle in one evaporator, exhibiting compatible low-threshold low-leakage saturating drain characteristics with several volts applied to drain and gate. In addition, photoprocessing methods have been successfully utilized in defining source-drain electrodes for p-type TFT's although less successfully for compatible n-type TFT's. These electrodes consist of 5-microns lines separated by 5-microns spaces, yielding short clean channels and potentially low gate loading capacitance. The resulting characteristics are similar to those of devices obtained by masked evaporation and indicate an effective 20 cm sq/V-sec mobility, an expected complementary inverter pair-delay of 30 nsec, and an attainable density of 1000 associative memory cells per square inch.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1968
- Accession Number
- AD0828570
Entities
People
- Abraham Harel
- James J. Gibson
- Joseph R. Burns
- Kuo-chen Hu
- Robert A. Powlus
Organizations
- Sarnoff Corporation