Silicon-on-Sapphire Transistor for Associative Processors.
Abstract
System, circuit, and device considerations are presented as an integral part of the realization of a 4-word, 4-bit associative memory array incorporating 224 complementary MOS transistors fabricated with a unique low-temperature processing sequence appropriate for silicon-on-sapphire technology. The basic cell is designed to operate as a read-write random access memory with nondestructive read-out in addition to high-speed parallel associative search capabilities. The array is completely modular in multiples of 4 words and 4 bits and generates a mismatch signal proportional to the number of bits in error in a given word. The associative cell can be written into in less than 10 nanoseconds, and produces a minimum read-out and mismatch signal of 1 mA. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 1969
- Accession Number
- AD0858368
Entities
People
- Joseph H. Scott
- Joseph R. Burns
Organizations
- Sarnoff Corporation