5-Kilowatt, 1-Kilovolt, Laminated Sonar Transistor.
Abstract
A basic change made in the processing technique to simplify and improve the process is described in detail. The mechanical processing steps, such as cavitronning, are performed presently from the collector side rather than from the emitter side. This has eliminated the need of a handle wafer, allowing the use of a shortened lamination cycle, and has resulted in more uniform electrical characteristics. Approximately 40 percent of the pellets pressed with the shortened cycle have had good electrical characteristics. A method of making collector contact after lamination is described. This greatly simplifies the processing of the base collector wafer. Only 0.7 mil of epitaxy is needed compared to more than 4 mils for a standard epitaxial pi-nu wafer with this voltage capability. An automatic cavitron alignment technique is also described. Initial results of high-current measurements on design IIIB and IIIC devices are given and indicate that emitter periphery is a more important factor in determining high-current performance than emitter area. Maximum collector current was 30 amps for the IIIB device compared to 18 amps for the IIIC device, which had 30 percent more emitter area but 40 percent less emitter periphery. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 1969
- Accession Number
- AD0863005
Entities
People
- Hans W. Becke
- Joseph P. White