Modeling of Logical Schemes on a Digital Computer,

Abstract

Known methods for the modeling and analysis of logical circuits either neglect the delay time within the individual elements or consider two types of elements with and without fixed delays. The presently described model allows the tracing of the states of logical circuits without limitation on the delay time within component elements. Experimental error-search in standard adders and registers by means of induced incorrect couplings and delays points to the feasibility of standard subprograms for the analysis and diagnostics of different logical schemes. (Author)

Document Details

Document Type
Technical Report
Publication Date
Jan 06, 1971
Accession Number
AD0886467

Entities

People

  • K. Boyanov
  • T. Velichkov

Organizations

  • National Air and Space Intelligence Center

Tags

DTIC Thesaurus Topics

  • Computers
  • Couplings
  • Digital Computers
  • Standards

Fields of Study

  • Physics

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computer Programming and Software Development.
  • Theoretical Analysis.