Techniques for Subnanosecond Logic.
Abstract
This report describes the design and development of a high speed multiplexing/demultiplexing system with digital circuits capable of operating at subnanosecond switching speeds and at serial data rates through 1 Gb/s. The equipment developed consists of a data pattern generator, a high speed 4-to-1 digital multiplexer, a high speed 1-to-4 digital demultiplexer, and an error correlator. The data pattern generator provides a 31-bit PRN data pattern (plus several other data patterns) and serves as a four line, 250 Mb/s per line data source for system test. The multiplexer multiplexes the 250 Mb/s parallel data to a serial data rate of 1 Gb/s. The demultiplexer accepts the 1 Gb/s serial NRZ data and demultiplexes it down to its original four lines at 250 Mb/s per line. The error correlator continually compares the multiplexed and demultiplexed data to detect and display bit errors on a bit-by-bit basis. Because the 1 Gb/s data rate was approximately four times faster than the fastest commercially available logic, special subnanosecond (differential emitter gated) logic circuits were developed in microelectronic hybrid form: latch flip-flop, multiplexer circuit, AND gate, and input/output buffer. These circuits exhibit switching speeds of 200 to 400 psec and propagation delays under 500 psec. The equipment was specifically designed to be a completely variable frequency multiplexing/demultiplexing system and was tested for bit error rate performance at frequencies up through 1 Gb/s.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1973
- Accession Number
- AD0908862
Entities
People
- Carl E. James
- Fred S. Carper
- Kenneth B. De Graaf
Organizations
- TRW Inc.