Side-Channel-Proof Circuit Design for Hardware Security

Abstract

This STIR project was highly successful. The team has significantly reduced the overhead of side-channel-proof Multi-Threshold Dual-Spacer, Dual-Rail, Delay-Insensitive (MTD3L) asynchronous logic, without compromising the resistivity against power-based side-channel attacks. The improvements of the new MTD3L architecture compared with the old MTD3L architecture in implementing an AES core is 353% in power, 388% in speed, and 546% in registration size.

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Document Details

Document Type
Technical Report
Publication Date
May 29, 2015
Accession Number
AD1001144

Entities

People

  • Di Jia

Organizations

  • University of Arkansas

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Abstracts
  • Agreements
  • Algorithms
  • Circuits
  • Computations
  • Cryptography
  • Department Of Defense
  • Energy Consumption
  • Engineering
  • Generators
  • Logic
  • Mathematics
  • Simulations
  • Students
  • Switching
  • Technology Transfer
  • Transistors

Fields of Study

  • Computer science

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Cybersecurity.
  • Electrical Engineering