Complementary Metal-Oxide-Silicon (CMOS)-Memristor Hybrid Nanoelectronics for Advanced Encryption Standard (AES) Encryption

Abstract

The objective of this effort was to develop and demonstrate CMOS-memristor hybrid nanoelectronic circuits produced in a standard CMOS foundry setting. Specifically, memristor nanodevices optimized for performance and reliability were developed and integrated with CMOS circuitry to establish an efficient hybrid nanoelectronic computing module for Advanced Encryption Standard (AES). This new hybrid CMOS/memristor technology will be available for future novel, emerging unconventional architecture with size, weight and power constraints. The deliverables under this effort were several dozen chips fabricated using the standard 10LPe (65 nm) CMOS transistor node integrated with the memristors without leaving the CMOS foundry setting.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 2016
Accession Number
AD1009567

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  • Nathaniel C Cady

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  • SUNY Polytechnic Institute

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