Cross-Layer Resilience Exploration

Abstract

Low-cost fault tolerance requires careful combination of fault tolerance techniques across all levels of the system stack. We describe a systematic framework, applicable to simple and complex cores as well as specialized accelerators, to explore this cross-layer design space in terms of area, power, and performance costs, and present illustrative results.

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Document Details

Document Type
Technical Report
Publication Date
Mar 31, 2015
Accession Number
AD1023378

Entities

People

  • Chen-yong Cher
  • Eric Cheng
  • Hyungmin Cho
  • Jacob A. Abraham
  • Kevin Skadron
  • Lukasz G. Szafaryn
  • Mircea R. Stan
  • Shahrzad Mirkhani
  • Subhasish Mitra

Organizations

  • Stanford University

Tags

Communities of Interest

  • Engineered Resilient Systems

DTIC Thesaurus Topics

  • Algorithms
  • Case Studies
  • Compilers
  • Computer Architecture
  • Computing System Architectures
  • Department Of Defense
  • Detection
  • Embedded Systems
  • Fault Tolerance
  • Hardening
  • Instructions
  • Micro-Machines
  • Pipelines
  • Radiation Hardening
  • Recovery
  • Reliability
  • Resilience

Readers

  • Computer Networking
  • Systems Analysis and Design

Technology Areas

  • Space