Modeling and Experiments with Carbon Nanotubes for Applications in High Performance Circuits
Abstract
The report is divided into the following two parts: carbon nanotube (CNT) based electronics and graphene (G) based electronics. In Part I, CNT based electronics, electrical model of CNT-Field-Effect Transistor (CNT-FET) has been developed from the device physics for analysis and design of very low-power integrated circuits. Current Complementary Metal Oxide Semiconductor (CMOS) technologies below 22nm nodes are plagued by the problems in copper interconnections due to its increased resistance and void formation. Exhaustive studies of single-wall CNT (SWCNT), multi-wall CNT (MWCNT) and bundle of single-wall CNTs have been conducted for short, local and global interconnects and choice of suitability of their integration is suggested. Since CNT breaks down in integration with CMOS due to self heating, an exhaustive study of self-heating effects in CNT has been conducted. In Part II, graphene-based electronics, analytical current transport model of graphene nanoribbon (GNR) tunnel-FET (GNR-TFET) has been developed for integration with design automation tools for design of graphene based integrated circuits. A BenchTop nanoCVD-8G System from Moorfield, Inc. UK has been purchased and installed for experimental characterization of atomic layer deposited graphene on different substrates for radiation-hardened studies.
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 06, 2017
- Accession Number
- AD1032703
Entities
People
- Ashok Srivastava
Organizations
- Louisiana State University