In-Storage Embedded Accelerator for Sparse Pattern Processing

Abstract

We present a novel architecture for sparse pattern processing, using flash storage with embedded accelerators. Sparse pattern processing on large data sets is the essence of applications such as document search, natural language processing, bioinformatics, subgraph matching, machine learning, and graph processing. One slice of our prototype accelerator is capable of handling up to 1TB of data, and experiments show that it can outperform C/C++ software solutions on a 16-core system at a fraction of the power and cost; an optimized version of the accelerator can match the performance of a 48-core server.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Aug 13, 2016
Accession Number
AD1032976

Entities

People

  • Arvind Mithal
  • Huy T. Nguyen
  • Sang-woo Jun
  • Vijay N. Gadepally

Organizations

  • MIT Lincoln Laboratory

Tags

Communities of Interest

  • Autonomy
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Artificial Intelligence
  • Artificial Intelligence Software
  • Computational Science
  • Computations
  • Computer Languages
  • Computer Science
  • Computers
  • Data Analysis
  • Data Management
  • Data Processing
  • Data Sets
  • Field Programmable Gate Arrays
  • Machine Learning
  • Mathematical Models
  • Neural Networks
  • Operating Systems
  • Sparse Matrix

Fields of Study

  • Computer science

Readers

  • Distributed Systems and Data Platform Development
  • Parallel and Distributed Computing.

Technology Areas

  • AI & ML