In-Storage Embedded Accelerator for Sparse Pattern Processing

Abstract

We present a novel system architecture for sparse pattern processing, using flash storage and an in-storage embedded accelerator. Placing commonly used computing kernels in direct access to a data source achieves high performance, without increasing the requirements for system memory. We show that the sparse pattern matching accelerator is useful for general sparse vector multiplication, feature matching, subgraph matching, protein database search, and machine learning applications. In our prototyping experiment, one accelerator slice can outperform a 16-core system at a fraction of the power and cost.

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Document Details

Document Type
Technical Report
Publication Date
Sep 13, 2016
Accession Number
AD1033701

Entities

People

  • Arvind Mithal
  • Huy T. Nguyen
  • Jun Sang-woo
  • Vijay N. Gadepally

Organizations

  • MIT Lincoln Laboratory

Tags

Communities of Interest

  • Autonomy
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Artificial Intelligence
  • Artificial Intelligence Software
  • Computational Science
  • Computations
  • Computer Architecture
  • Computer Languages
  • Computer Science
  • Computers
  • Computing System Architectures
  • Data Analysis
  • Data Management
  • Field Programmable Gate Arrays
  • Machine Learning
  • Mathematical Models
  • Measurement
  • Neural Networks

Fields of Study

  • Computer science

Readers

  • Neural Network Machine Learning.
  • Parallel and Distributed Computing.

Technology Areas

  • AI & ML