Modeling of a Stacked Power Module for Parasitic Inductance Extraction
Abstract
Power switching modules inevitably suffer from compromised electrical performance due to limitations imposed by standard planar packaging arising from issues of heat dissipation, reliability, and parasitic inductance. An improved packaging approach has been proposed to simultaneously address each of these issues, including parasitic inductance. Parasitic inductance has a particularly detrimental effect on metal oxide semiconductor field-effect transistor switching characteristics due to signal overshoot. This approach makes use of multifunctional components as concurrent electrical, thermal, and mechanical attachments. The power devices in the resulting module design are stacked between copper layers with an integrated heat sink. By stacking devices, the modules parasitic inductance should be reduced, with concurrent improvement of reliability and heat dissipation, in comparison to traditional planar packaging. This report describes modeling used to extract the predicted parasitic inductance of a stacked half-bridge switching module, by performing magnetic-field simulations to derive frequency-dependent impedances.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 15, 2017
- Accession Number
- AD1039284
Entities
People
- Steven Kaplan
Organizations
- United States Army Research Laboratory