Building a Library for Microelectronics Verification with Topological Constraints

Abstract

This paper proposes a methodology to build a library for gate-level microelectronics verification with topological constraints. Circuits at the second level of abstraction are selected from prior work on simulated reverse-engineered hardware. We show that when signal pairs are switched while maintaining circuit functionality, the topological genus varies according to a frequency distribution that differs for each circuit.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 2017
Accession Number
AD1041375

Entities

People

  • Derrick Langley
  • Graziano Vernizzi
  • Leleia A. Hsia
  • Mary Lanzerotti

Organizations

  • 513th Electronic Warfare Squadron

Tags

Communities of Interest

  • Air Platforms

DTIC Thesaurus Topics

  • Air Force
  • Circuits
  • Department Of Defense
  • Electrical Properties
  • Electronic Warfare
  • Engineering
  • Equivalent Circuits
  • Frequency
  • Integrated Circuits
  • National Security
  • Permutations
  • Switches
  • Three Dimensional
  • Two Dimensional
  • United States
  • Universities
  • Xor Gates

Fields of Study

  • Engineering

Readers

  • Database Systems and Applications
  • Integrated Circuit Design and Technology.
  • Regression Analysis.

Technology Areas

  • Microelectronics
  • Microelectronics - Graphene