Side Channel Attacks on STTRAM and Low Overhead Countermeasures
Abstract
Spin-Torque Transfer RAM (STTRAM), although promising, suffers from high write latency and write current. Additionally, the latency and current depends on the polarity of the data being written. These factors introduce security vulnerabilities and expose the cache memory to side channel attacks. In this paper, we propose a side channel attack (SCA) model where the adversary can monitor the supply current of the memory array to partially identify the sensitive cache data that is being read or written. We propose solutions such as short retention STTRAM, obfuscation of SCA using 1-bit parity, multi-bit random write, and, neutralizing the SCA using constant current write driver to mitigate such attacks.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 20, 2017
- Accession Number
- AD1041841
Entities
People
- Anirudh Iyengar
- Swaroop Ghosh
Organizations
- Pennsylvania State University