A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers
Abstract
This report summarizes a year-long study on the applicability of the charge trap transistor (CTT) for embedded memory applications. Two case uses are considered (1) as a digital multi-time programmable memory and (2) as are programmable analog memory. Experimental data reveals that a CTT for analog memory applications possesses promising characteristics for implementing synapses in neural networks, such as spike-timing dependent plasticity, very fine tunability, weight-dependent plasticity, and low power consumption. Ongoing efforts include the design and tape out of a CTT-based neuromorphic chip for digit recognition, and more elaborate designs that address programming time, scalability, power/area reduction, redundancy, unsupervised learning, etc. in the long-term.
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 01, 2018
- Accession Number
- AD1050743
Entities
People
- Subramanian Iyer
Organizations
- University of California, Los Angeles