Revolutionizing System Validation Post-Manufacture

Abstract

To automatically verify and debug future systems (including both new and upgraded systems), our approach consists of two major parts. The first quickly (and automatically) detecting difficult bugs with Quick Error Detection (QED), shortening error detection latencies by several orders of magnitude (to only a few clock cycles). The second provides a framework for localizing bugs, with Symbolic QED and E-QED. These techniques demonstrate that for difficult bugs in large designs that would traditionally take weeks or months to debug, we can identify the causes of logic and electrical bugs within hours.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jul 01, 2018
Accession Number
AD1056766

Entities

People

  • Subhasish Mitra

Organizations

  • Stanford University

Tags

Communities of Interest

  • Advanced Electronics
  • Autonomy

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Algorithms
  • Consistency
  • Debugging
  • Detection
  • Error Analysis
  • Frequency
  • Government Procurement
  • Governments
  • Information Exchange
  • Instructions
  • Language
  • Machine Learning
  • Simulations
  • Validation
  • Verification

Fields of Study

  • Computer science

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Distributed Systems and Data Platform Development
  • Software Engineering