Energy Efficient Signal Processing on 3D Memory Integrated Multi-Core Platforms

Abstract

The Air Force Research Laboratory (AFRL) is developing a secure processor that integrates a multicore logic layer with vertically stacked DRAM. The chief advantage of such 3D Memory Integrated architectures is the large amounts of memory accessible by the on-chip logic via high bandwidth vertical interconnects. While the energy cost of block memory access can be well defined in such a platform, there is currently no method of optimizing the memory accesses of a complex algorithm and its impact on energy consumption in platforms with 3D stacked memory. In particular, the high bandwidth connection between logic and memory in 3D architectures has created an opportunity to redesign the conventional processor-memory cache hierarchy with potentially significant effect on both kernel performance and overall energy efficiency. Mapping applications to this target platform is therefore complex due to the large number of architectural features and their complex performance-energy-efficiency tradeoffs. In this project, we developed a performance model of the Target 3D Memory Integrated Multicore Platform that can be used for evaluating the energy-efficiency and performance-energy tradeoffs of specific signal processing algorithms as mapped onto this target platform. We then demonstrated the efficiency of this framework by mapping representative signal processing kernels and generating design curves describing the tradeoff between energy efficiency and algorithm performance. Our results enable the principled and practical exploration of parallel algorithm performance and energy-efficiency and understanding of the impact of architectural design choices on performance-energy tradeoffs, which is central to the adoption of 3D memory, centered platforms in C4ISR applications.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 2018
Accession Number
AD1057985

Entities

People

  • Viktor K. Prasanna

Organizations

  • University of Southern California

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Algorithms
  • Bandwidth
  • Circuits
  • Computer Architecture
  • Computers
  • Computing System Architectures
  • Efficiency
  • Energy Consumption
  • Energy Efficiency
  • Equations
  • Field Programmable Gate Arrays
  • Hierarchies
  • Integrated Circuits
  • Military Research
  • Networks
  • Parallel Computing
  • Processing Equipment
  • Signal Processing
  • Three Dimensional
  • Three Dimensional Integrated Circuits
  • United States
  • Very Large Scale Integration

Fields of Study

  • Computer science
  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.
  • Systems Analysis and Design