Implementation Of The Fast Fourier Transform Onboard CFTP-7 Space Experiment
Abstract
A satellite to be used as a testbed for experiments such as the Configurable Fault Tolerant Processor (CFTP) was designed at the Naval Postgraduate School. This processor consists of a Field Programmable Gate Array (FPGA), which may be reprogrammed by receiving a signal from a source external to the satellite. Experimentation of a high-speed pipelined and fault tolerant Fast Fourier Transform (FFT) was conducted for use within the CFTP. In this thesis, we detail the development and testing of a high-speed pipelined FFT in which fault tolerance can be applied at a later opportunity. Xilinx Vivado ISE(registered trademark) was utilized to synthesize behavioral Verilog to program an FPGA. Xilinx Vivado ISEs(registered trademark) simulation suite produced waveforms to demonstrate functionality. Launch of CFTP is planned for FY18 aboard NPSat-1.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 2018
- Accession Number
- AD1060098
Entities
People
- Alan Walker
Organizations
- Naval Postgraduate School